10/4/2023 Jenny Applequist
Under a $2 million Future of Semiconductors (FuSe) grant from the National Science Foundation, a new project led by Qing Cao will bring together experts from all domains in microelectronics to develop a cost-effective architecture that is built on novel artificial synaptic transistors to enable continuous learning on edge devices, with unprecedented capabilities and energy efficiency.
Written by Jenny Applequist
Billions of edge devices have been deployed worldwide, but in the age of AI, their capabilities are sharply constrained by their limited energy and computing resources.
Now, under a $2 million Future of Semiconductors (FuSe) grant from the National Science Foundation, a new project led by Qing Cao will bring together experts from all domains in microelectronics to develop a cost-effective architecture that is built on novel artificial synaptic transistors to enable continuous learning on edge devices, with unprecedented capabilities and energy efficiency.
Cao, who is an associate professor of Materials Science & Engineering, Chemistry, and Electrical & Computer Engineering (ECE), recently explained that the major research focus will be on making machine learning more efficient for mobile devices, such as self-driving cars, rather than for data centers. The goal is to greatly improve devices’ ability to learn about and adapt to their environments without relying on communications with centralized servers, as such communications are unreliable, consume energy, incur delays, and raise security concerns.
“To make it happen, we need a joint effort across different layers,” said Cao. “We need better materials, we need more energy-efficient new analog memory device concepts, and also we need to put those devices into functional circuit architectures and run a new type of machine learning algorithm, designed with the unique characteristics of our new hardware in mind.”
He noted that the novel ECRAM memory devices he’s been working on can’t yet compete with existing silicon solutions in terms of operating speed. That’s why this project will focus on edge devices rather than centralized servers.
“We think those niche markets where the energy consumption and the chip-area cost are more important compared to the operating speed—that’s going to be our starting point,” he said. “That’s an area where we think we’re going to maximize our benefit and still mitigate our disadvantages compared to state-of-art silicon CMOS.”
The team will also engage in education and outreach activities that include pilot efforts to address key aspects of the workforce shortfall in the semiconductor industry—such as a lack of workers for jobs at the technician level.
“There’s going to be a strong demand for students at the Ph.D. level to support research and development,” said Cao. “But at the same time, they actually also need students, maybe with associate’s degrees from the community college level, to serve as technicians or process engineers.”
The problem, he explained, is that community colleges don’t have the facilities or expertise to train students to work in microelectronics, despite surging demand from semiconductor foundries that are investing heavily in the Midwest, thanks to the CHIPS and Science Act.
Therefore, Cao’s team will pilot a novel training program wherein students from Parkland College—a public community college in Champaign, Illinois—will pursue a four-week summer training experience in UIUC campus facilities, culminating in a certificate and access to the Grainger College of Engineering’s career placement services.
Cao said that if the program is successful, it can serve as a model for other institutions wanting to build microelectronics partnerships between community colleges and research universities.
The team will also pursue innovative educational activities at the university level. For example, they will develop new curricula for UIUC and University of Illinois Chicago courses to ensure that computer science students gain the deeper understanding of devices that they will need to advance the frontiers of microelectronics.
The co-principal investigators on the project, which is entitled “Co-designing Continual-Learning Edge Architectures with Hetero-Integrated Silicon-CMOS and Electrochemical Random-Access Memory,” are Shaloo Rakheja of ECE; Saugata Ghose of Computer Science; Curtis Shoaf of Parkland College; and Amit Trivedi of the University of Illinois Chicago.
The project is one of two new FuSe awards with UIUC participation. The other, led by Washington University in St. Louis, is “Metaoptics-Enhanced Vertical Integration for Versatile In-Sensor Machine Vision.” It will investigate an AI-driven vision system that can be tailored for domain-specific problems, such as environmental monitoring or visual adaptivity for self-driving cars. The UIUC portion of that project will be led by ECE professor Viktor Gruev.