Materials Science and Engineering Special Seminar


Dr. Qing Cao, IBM Thomas J. Watson Research Center, Yorktown Heights, NY

Date Tue, 01/23/2018

280 Materials Research Laboratory

Time 8:30 am

Materials Science and Engineering

Event Type Seminar/Symposium

“Carbon nanotube transister technology for extremely-scaled logic devices”


Conventional scaling of Si complementary metal-oxide semiconductor devices as described by Moore’s law provided exponentially improving transistor performance, density, power, and cost in the last five decades.  However, it has become increasingly difficult in recent 10 years with Si devices approaching their physical limits.  In search for the next switch beyond silicon, carbon nanotubes are a very promising candidate.  In this talk, I will review our recent efforts at IBM on developing carbon nanotube transistor technology for the next-generation logic chips.  I will first discuss why the unique material properties of carbon nanotubes, including their intrinsic thinness (about 1 nm in diameter), high carrier saturation velocity, and capability to form low-resistance, end-bonded contacts, are critical for device scaling from industrial perspective.  Our recent results further proved in experiment the combination of all these attributes indeed leads to substantially improved performance of extremely-scaled nanotube transistors down to merely 40 nm overall footprint compared to what is possible with Si.  Moreover, recent progress on the purification of semiconducting nanotubes to purity above 99.999%, and their subsequent assembly into well-aligned arrays with unprecedented high nanotube density allowed us to demonstrate the first nanotube-array transistor to outperform their best-competing silicon devices in on-state conductance without any normalization.  These results suggest that replacing Si with carbon nanotubes in high-performance logic device at the 5-nm technology node and beyond is not only physically plausible but also technically feasible.  Currently the major obstacle is reducing the device variability.  Scientific understanding of its major source provides guideline to rationally address this challenge with materials and engineering innovations.  A concluding discussion provides perspectives on the future of carbon nanotube based nanoelectronics.